The present invention concerns a technique for use in the manufacture of a semiconductor integrated circuit device; and, more in particular, it relates to a technique that is effective when applied to a step of forming, in an identical interconnection layer on a semiconductor substrate, plural interconnections at a narrow distance, which distance is smaller than the resolution limit for the exposure light used in a photolithography step employed in semiconductor manufacture.
Along with refinement of semiconductor integrated circuits, since the pattern size, for example, of electrode interconnections formed over semiconductor substrates have already reached the resolution limit of the exposure light used in the photolithographic step employed in semiconductor manufacture, a phase shift technique or a multiple exposure technique, which is capable of forming such interconnections at a pattern size smaller than the resolution limit of the exposure light, have been adopted.
The multiple exposure technique is a technique in which exposure is repeated plural times using plural sheets of photomasks, thereby transferring a pattern With a size smaller than the resolution limit of the exposure light to a photoresist film on a semiconductor substrate, as disclosed, for example, in the below-listed Patent Documents 1 to 3.
For example, Patent Document 1 discloses a quadplex exposure technique of conducting duplicate exposure to a photoresist film by using first and second photomasks, with the positions for a shield pattern and a phase shift pattern being replaced with each other, and then conducting exposure to the photoresist film by using third and fourth photomasks, with the positions for the patterns being different from those of the first and second photomasks and the positions for the shield pattern and the phase shift pattern being replaced with each other, thereby transferring a pattern at a size smaller than the resolution limit of the exposure light.    [Patent Document 1]    Japanese Patent Application laid-open No. Hei 8 (1996)-45834    [Patent Document 2]    Japanese Patent Application laid-open No. 2002-134394    [Patent Document 3]    Japanese Patent Application laid-open No. 2002-258462